### Abstract

As applications of the Self-Organising Map emerge in portable devices, power dissipation becomes a crucial design issue. The digital implementation of the SOM which is introduced in this paper meets low power requirements by means of increasing silicon area while reducing the number of clock cycles required to process each element of an input vector. Designs of a single neuron requiring two clock cycles, one clock cycle, and 1/2 clock cycle per element of the input vector are presented. The designs offer a reduction in power of a factor of 3 for an increase in silicon area of some 33%. The contribution of each routine composing training and classification to total power is also illustrated.

Original language | English |
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Pages (from-to) | 721-728 |

Number of pages | 7 |

Journal | Lecture Notes in Computer Science |

Volume | 2714 |

Publication status | Published - 2003 |

### Cite this

*Lecture Notes in Computer Science*,

*2714*, 721-728.

**Low power digital neuron for SOM implementations.** / Cambio, R.; Hendry, David Cyril.

Research output: Contribution to journal › Article

*Lecture Notes in Computer Science*, vol. 2714, pp. 721-728.

}

TY - JOUR

T1 - Low power digital neuron for SOM implementations

AU - Cambio, R.

AU - Hendry, David Cyril

PY - 2003

Y1 - 2003

N2 - As applications of the Self-Organising Map emerge in portable devices, power dissipation becomes a crucial design issue. The digital implementation of the SOM which is introduced in this paper meets low power requirements by means of increasing silicon area while reducing the number of clock cycles required to process each element of an input vector. Designs of a single neuron requiring two clock cycles, one clock cycle, and 1/2 clock cycle per element of the input vector are presented. The designs offer a reduction in power of a factor of 3 for an increase in silicon area of some 33%. The contribution of each routine composing training and classification to total power is also illustrated.

AB - As applications of the Self-Organising Map emerge in portable devices, power dissipation becomes a crucial design issue. The digital implementation of the SOM which is introduced in this paper meets low power requirements by means of increasing silicon area while reducing the number of clock cycles required to process each element of an input vector. Designs of a single neuron requiring two clock cycles, one clock cycle, and 1/2 clock cycle per element of the input vector are presented. The designs offer a reduction in power of a factor of 3 for an increase in silicon area of some 33%. The contribution of each routine composing training and classification to total power is also illustrated.

M3 - Article

VL - 2714

SP - 721

EP - 728

JO - Lecture Notes in Computer Science

JF - Lecture Notes in Computer Science

SN - 0302-9743

ER -