Low power digital neuron for SOM implementations

R. Cambio, David Cyril Hendry

Research output: Contribution to journalArticle

Abstract

As applications of the Self-Organising Map emerge in portable devices, power dissipation becomes a crucial design issue. The digital implementation of the SOM which is introduced in this paper meets low power requirements by means of increasing silicon area while reducing the number of clock cycles required to process each element of an input vector. Designs of a single neuron requiring two clock cycles, one clock cycle, and 1/2 clock cycle per element of the input vector are presented. The designs offer a reduction in power of a factor of 3 for an increase in silicon area of some 33%. The contribution of each routine composing training and classification to total power is also illustrated.

Original languageEnglish
Pages (from-to)721-728
Number of pages7
JournalLecture Notes in Computer Science
Volume2714
Publication statusPublished - 2003

Cite this

Cambio, R., & Hendry, D. C. (2003). Low power digital neuron for SOM implementations. Lecture Notes in Computer Science, 2714, 721-728.