On solving partition driven standard cell placement problem using firefly-based metaheuristic approach

The standard-cell placement problem has drawn great attention in the VLSI CAD domain. Being an NP complete problem, a spacious range of heuristic approaches exist in the literature for expeditiously organising the circuit elements on a VLSI chip design. The advancement in the partitioning algorithms has made the recursive bisection-based placement more attractive. The paper presents a metaheuristic approach based on firefly algorithm for partition-driven global standard cell placement. The algorithm is tested against circuits from the MCNC and IBM benchmark circuits and gives promising results in comparison to meta genetic approach.