@inproceedings{a4402b2949ed4484aeb88b0874fd1c3a,
title = "A discrete firefly algorithm for VLSI circuit partitioning",
abstract = "The CAD industries are facing a big challenge to meet the time-to-market and quality requirements. The complexity of physical design process has drastically increased due to exponential growth in the transistor count and heterogeneity of circuit elements on single chip. There is a stressing demand on CAD industry for developing faster and efficient techniques for VLSI physical design automation. This paper presents a swarm based heuristic approach for solving balanced min cut circuit partitioning the very first step of VLSI physical design automation.",
keywords = "Balance constraints, Circuit partitioning, Evolutionary firefly algorithm, VLSI circuits",
author = "Sharma, {Pradip Kumar} and Maninder Kaur",
year = "2014",
month = feb,
day = "14",
doi = "10.1109/ECS.2014.6892764",
language = "English",
series = "2014 International Conference on Electronics and Communication Systems, ICECS 2014",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2014 International Conference on Electronics and Communication Systems, ICECS 2014",
address = "United States",
note = "2014 International Conference on Electronics and Communication Systems, ICECS 2014 ; Conference date: 13-02-2014 Through 14-02-2014",
}