A discrete firefly algorithm for VLSI circuit partitioning

Pradip Kumar Sharma*, Maninder Kaur

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

The CAD industries are facing a big challenge to meet the time-to-market and quality requirements. The complexity of physical design process has drastically increased due to exponential growth in the transistor count and heterogeneity of circuit elements on single chip. There is a stressing demand on CAD industry for developing faster and efficient techniques for VLSI physical design automation. This paper presents a swarm based heuristic approach for solving balanced min cut circuit partitioning the very first step of VLSI physical design automation.

Original languageEnglish
Title of host publication2014 International Conference on Electronics and Communication Systems, ICECS 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781479923205
DOIs
Publication statusPublished - 14 Feb 2014
Event2014 International Conference on Electronics and Communication Systems, ICECS 2014 - Coimbatore, India
Duration: 13 Feb 201414 Feb 2014

Publication series

Name2014 International Conference on Electronics and Communication Systems, ICECS 2014

Conference

Conference2014 International Conference on Electronics and Communication Systems, ICECS 2014
CountryIndia
CityCoimbatore
Period13/02/1414/02/14

Keywords

  • Balance constraints
  • Circuit partitioning
  • Evolutionary firefly algorithm
  • VLSI circuits

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