A simulation and evaluation scheme for Single Event Effects in VLSI

Yufan Lu, Xin Chen, Xiaojun Zhai, Sangeet Saha, Shoaib Ehsan, Jinya Su, Klaus McDonald-Maier

Research output: Chapter in Book/Report/Conference proceedingPublished conference contribution


Due to the complexity of large scale integrated circuits, it can become time consuming to analyse Single Event Effect (SEE) in large circuits. Hence, this paper proposes a rapid
simulation scheme for large scale circuits. It takes advantage of transistor simulation tools and VLSI digital simulation tools to achieve both high accuracy and efficiency. The experiment results
show that one million SEEs can be injected into the S27 circuit in 55 s, while the HSPICE simulation takes 67000 times longer
Original languageEnglish
Title of host publicationAMICSA 2021
Publication statusPublished - 21 May 2021


  • Single event effect
  • fault injection
  • SEE model
  • SEE mitigation
  • HDL simulation
  • VLSI


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