Software Defined Radio (SDR) technology seeks to solve the problem of multiple incompatible broadcast/telecom standards available in different locations, by having standard specific processing defined in software. This software will be downloaded and run on generic hardware, so that different broadcast/telecom standards can be supported by downloading corresponding software modules. Computing platform based SDR attempts to bridge the worlds of computing and broadcast/telecoms, by exposing the features and resources of computers to SDR and vice versa. However, such a concept results in certain architectural issues that need to be resolved. This paper describes the concept of Computing Platform based SDR, and the resulting issues & desired features of such a system. An innovative system architecture that involves the supervised partial self-reconfiguration of a single FPGA is proposed and detailed. Finally, a system test is conducted to illustrate and verify the reconfiguration operation.
|Number of pages||1|
|Publication status||Published - 22 Apr 2003|
|Event||International Parallel and Distributed Processing Symposium (IPDPS'03), 2003 - Nice, France|
Duration: 22 Apr 2003 → 25 Apr 2003
|Conference||International Parallel and Distributed Processing Symposium (IPDPS'03), 2003|
|Period||22/04/03 → 25/04/03|
Faust, O., Sputh, B., Nathan, D., Rezgui, S., Weisensee, A., & Allen, A. R. (2003). A Single-Chip Supervised Partial Self-Reconfigurable Architecture for Software Defined Radio. 191a. Abstract from International Parallel and Distributed Processing Symposium (IPDPS'03), 2003, Nice, France.