A Single-Chip Supervised Partial Self-Reconfigurable Architecture for Software Defined Radio

O. Faust, B. Sputh, D. Nathan, S. Rezgui, A. Weisensee, Alastair Robert Allen

Research output: Contribution to conferenceAbstract

4 Citations (Scopus)

Abstract

Software Defined Radio (SDR) technology seeks to solve the problem of multiple incompatible broadcast/telecom standards available in different locations, by having standard specific processing defined in software. This software will be downloaded and run on generic hardware, so that different broadcast/telecom standards can be supported by downloading corresponding software modules. Computing platform based SDR attempts to bridge the worlds of computing and broadcast/telecoms, by exposing the features and resources of computers to SDR and vice versa. However, such a concept results in certain architectural issues that need to be resolved. This paper describes the concept of Computing Platform based SDR, and the resulting issues & desired features of such a system. An innovative system architecture that involves the supervised partial self-reconfiguration of a single FPGA is proposed and detailed. Finally, a system test is conducted to illustrate and verify the reconfiguration operation.
Original languageEnglish
Pages191a
Number of pages1
Publication statusPublished - 22 Apr 2003
EventInternational Parallel and Distributed Processing Symposium (IPDPS'03), 2003 - Nice, France
Duration: 22 Apr 200325 Apr 2003

Conference

ConferenceInternational Parallel and Distributed Processing Symposium (IPDPS'03), 2003
CountryFrance
CityNice
Period22/04/0325/04/03

Fingerprint

Reconfigurable architectures
Field programmable gate arrays (FPGA)
Hardware
Processing

Cite this

Faust, O., Sputh, B., Nathan, D., Rezgui, S., Weisensee, A., & Allen, A. R. (2003). A Single-Chip Supervised Partial Self-Reconfigurable Architecture for Software Defined Radio. 191a. Abstract from International Parallel and Distributed Processing Symposium (IPDPS'03), 2003, Nice, France.

A Single-Chip Supervised Partial Self-Reconfigurable Architecture for Software Defined Radio. / Faust, O.; Sputh, B.; Nathan, D.; Rezgui, S.; Weisensee, A.; Allen, Alastair Robert.

2003. 191a Abstract from International Parallel and Distributed Processing Symposium (IPDPS'03), 2003, Nice, France.

Research output: Contribution to conferenceAbstract

Faust, O, Sputh, B, Nathan, D, Rezgui, S, Weisensee, A & Allen, AR 2003, 'A Single-Chip Supervised Partial Self-Reconfigurable Architecture for Software Defined Radio' International Parallel and Distributed Processing Symposium (IPDPS'03), 2003, Nice, France, 22/04/03 - 25/04/03, pp. 191a.
Faust O, Sputh B, Nathan D, Rezgui S, Weisensee A, Allen AR. A Single-Chip Supervised Partial Self-Reconfigurable Architecture for Software Defined Radio. 2003. Abstract from International Parallel and Distributed Processing Symposium (IPDPS'03), 2003, Nice, France.
Faust, O. ; Sputh, B. ; Nathan, D. ; Rezgui, S. ; Weisensee, A. ; Allen, Alastair Robert. / A Single-Chip Supervised Partial Self-Reconfigurable Architecture for Software Defined Radio. Abstract from International Parallel and Distributed Processing Symposium (IPDPS'03), 2003, Nice, France.1 p.
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