Abstract
This paper describes the column oriented butted regular architecture-algorithmic behavioral synthesis (COBRA-ABS) high-level synthesis tool which has been designed to synthesize DSP algorithms, specified in C, onto multi-field programmable gate array (FFGA) custom computing machines (FCCMs). COBRA-ABS performs synthesis using a new simulated annealing-based methodology, which maps the specified behavior into a four-dimensional (4-D) space and then optimizes the implied architecture. COBRA-ABS synthesizes custom very long instruction word (VLIW) style architectures partitioned across the FPGAs of the FCCM and has been used to compile C algorithms down to FPGA configuration bit-streams, This paper describes the tool and synthesis concepts and presents simulation results from a number of synthesized fast Fourier transform (FFT) related algorithms.
Original language | English |
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Pages (from-to) | 218-223 |
Number of pages | 5 |
Journal | IEEE Transactions on Very Large Scale Integration Systems |
Volume | 9 |
Issue number | 1 |
DOIs | |
Publication status | Published - Feb 2001 |
Keywords
- allocation
- compiler
- custom computing
- DSP synthesis
- FCCM
- field programmable gate array (FPGA) synthesis
- high-level synthesis
- partitioning
- scheduling
- simulated annealing
- VLIW